Monte Carlo Analysis of the Dynamic Behavior of InAlAs/InGaAs Velocity Modulation Transistors: A Geometrical Optimization

Abstract

The influence of the geometry on the dynamic behavior of InAlAs/InGaAs velocity modulation transistors is analyzed by means of a Monte Carlo simulator in order to optimize the performance of this new type of transistor. In velocity modulation transistors, based on the topology of a double-gate high electron mobility transistor, the source and drain electrodes are connected by two channels with different mobilities, and electrons are transferred between both of them by changing the gate voltages in differential mode. Consequently, the drain current is modulated while keeping the total carrier density constant, thus in principle avoiding capacitance charging/discharging delays. However, the low values taken by the transconductance, as well as the high capacitance between the two gates in differential-mode operation, lead to a deficient dynamic performance. This behavior can be geometrically optimized by increasing the mobility difference between the two channels, by increasing the channel width and, mainly, by reducing the gate length, with a higher immunity to short channel effects than the traditional architectures.