Desing optimization of AlInAs/GalnAs HEMTs for low-noise applications

Abstract

Segunda parte del estudio basado en simulaciones Monte Carlo de HEMTs de InGaAs con 50nm de longitud de puerta. En este caso se estudia el efecto sobre el ruido del nivel de dopaje delta, de la anchura de los transistores y también de la longitud del recess. El efecto sobre el ruido del dopaje delta y de la anchura es similar al que tienen sobre ft y fmax, deteriorándose al elevar ambos. Además, hemos confirmado que la reducción de la longitud del recess tiene un efecto beneficioso sobre el ruido de los HEMTs.

In order to optimize the low-noise performance of 50-nm-gate AlInAs/GaInAs HEMTs, by using an ensemble Monte Carlo simulation we study the influence of three important technological parameters on their noise level: the doping of the ?-doped layer, the width of the devices and the length of the recess. The noise behavior of the devices is firstlyanalyzed in terms of the physics-based P, R and C parameters, and then characterized from a practical (circuit oriented) point of view through their four noise parameters: minimum noise figure, Fmin, noise resistance, Rn, and complex input admittance, Yopt (or reflection coefficient, ?opt). We have observed an enhancement of the noise when the??doping or the device width are increased (a deterioration parallel to that of fmax).Thus, the optimum noise operation is obtained for the lowest possible values of the ??doping and device width. However, for small width the effect of the offset parasitic capacitances makes Fmin increase, thus imposing a limit for the reduction of the noise.Moreover, the increase of Rn for small W makes the noise tuning condition critical to reach the optimum low-noise operation. We have also confirmed that when shortening the recess length from 100 nm to 20 nm at each side of the gate Fmin is reduced, with a slight deterioration of fmax, while the static characteristics are not modified.